1. Technical Field of the Invention
The present invention relates generally to semiconductor memories. More particularly, and not by way of any limitation, the present invention is directed to a system and method for repairing a memory instance.
2. Description of Related Art
Typically, memories are tested and repaired by serially transmitting commands from a built-in self-test (BIST) interface that is clocked with a test clock and then allowing the memory to perform a read or write operation. A processor, called a BIST processor, is usually provided for effectuating the testing operations. When several memory instances are interfaced with a single BIST processor, the serial command transfer process is slow and significantly limited by the delays inherent in the long signal paths necessitated by design and layout constraints. Accordingly, the memory testing operations are executed at a slower frequency than the clock frequency associated with the memory. Additionally, the BIST processor has to take a finite number of test clock cycles for each operation in order to send all commands serially, thereby substantially impacting the testing performance.
Furthermore, the conventional BIST processor arrangement is also fraught with several shortcomings and drawbacks with respect to memory repair. For instance, after the BIST processor completes the test algorithm, the failure data is scanned out by the BIST processor and provided to an external tester with additional intelligence. The failure data, which contains location information such as faulty row or faulty column address information, is post-processed by the tester software to create a repair bit signature that is fed back to the BIST processor. It should be appreciated that the whole process of repair bit generation takes several BIST clock cycles, not to mention the requirement of external tester intelligence to post-process the failure data for creating the requisite repair signature based on the memory array size, column MUX options, and the like. If the memory device has more errors than the repair elements, then the external tester needs additional intelligence to determine fatal errors, which can be time-consuming and cumbersome.